An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems

摘要

This work presents a novel control loop concept to adjust dynamically a differential ring oscillators (DRO) biasing in order to improve the phase noise performance (PN) in the ultra-low-power domain. Applying this proposed feedback system on any DRO with a tail current source is possible. The following paper presents the proposed concept and includes measurements of a 180 nm CMOS integrated prototype system, which underlines the feasibility of the discussed idea. Measurements show an up to 35 dBc/Hz phase noise improvement with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by about 430 % compared to hxed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz.