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Wirability of logic circuit packages in LSI and VLSI

机译:LSI和VLSI逻辑电路包的可线性

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摘要

The problems of designing and manufacturing systems made from integrated circuits have been changing rapidly as semiconductor technology has made greater circuit densities possible. Because of this rapid rate of change and the short time available for system design, it is essential to have reasonably accurate preliminary estimates of logic circuit counts, package sizes, and costs, as well as of design schedules. By preliminary, we mean prior to availability of circuit level system logic designs and/or prior to availability of partitioning, placement, and wiring aids to layout in a particular technology. The problem is complicated by the difference in difficulty between the predictability of wiring demand on packages with regular arrays of logic carriers and packages containing variably sized and shaped groups of logic circuits. Methods have been developed for preliminary estimation of wiring capacity in both these situations, and both methods and results will be discussed.
机译:随着半导体技术使电路密度更大的电路密度,集成电路制造的设计和制造系统的问题已经迅速变化。由于这种快速的变化率和系统设计的短时间,因此必须合理准确地准确初步估计逻辑电路计数,包装尺寸和成本以及设计时间表。通过初步,我们的意思是在电路级系统逻辑设计和/或在特定技术中布局的分区,放置和接线辅助装置之前的可用性之前。在逻辑载波的常规阵列和包含可变大小的逻辑电路组的套路阵列的套件的预测性与套件阵列的封装的可预测性之间的难度差异的差异是复杂的。已经开发了用于初步估计这些情况的布线容量的方法,并且将讨论方法和结果。

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