Fixed-width multiplier for DSP application

摘要

A new compensation method that reduces the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.