A design methodology for a fully synthesized high speed DSP core In A deep sub-micron technology

摘要

We present a design methodology that was used to design a 150MHz DSP core in a deep submicron technology, with emphasis on high speed and fast design cycle time. We detail the methodology, primarily based on synthesis, describe how we coupledsynthesis to placement and layout and present data on our timing convergence results. We present data on experiments that we performed to tune specific steps of the methodology, which were critical to make the methodology successful.