Design of a Compact Power Amplifier with 18.6 dBm 60 GHz 20.5 PAE in 22 nm FD-SOI

摘要

This paper presents the design of a 60 GHz power amplifier (PA) in a 22 nm FD-SOI CMOS technology. To improve the performance at millimeter-wave frequencies by minimizing the parasitics around transistors, a compact gain cell layout is proposed, which also integrates neutralization capacitors. By utilizing two cascode stages the gain has achieved 30 dB. The PA delivers a saturated output power of 18.6 dBm at 60 GHz, while drawing only 351mW from a supply voltage of 1.8 V, corresponding to a peak power added efficiency (PAE) of 20.5 %. Benefit from the compact transformers for impedance matching the active circuit area is reduced to 166 um x 424 um = 0.07 mm^{2, which gives this PA one of the highest output power to area ratio $(rac{Psat}{Area})$ among the state-of-the-art.}