Facing the difficulty to reach the International TechnologyRoadmap (ITRS) in junction technology with the conventional approachnumerous alternative doping processes have been recently developed tofabricate very-well activated and shallow p+ junctions.Taking into account that such processes present many challenges to solvefor their integration, we choose to re-examine, in this paper, the ITRStargets. We show that the series resistance requirements can be achievedwith the usual processes (ion implantation and rapid thermal annealing)for the 100 nm node. Furthermore, we demonstrate that the ITRS processwindow can be enlarged toward shallower junctions with relaxed sheetresistance. For sub-100 nm technologies, we identify the integrationprocess issues for the usual doping processes. Tied with the anomalousdiffusion of the implanted boron profile tail during the spacerdeposition in one hand, with the coupled diffusion due to thesource/drain implants in the other hand, we propose the Plasma Doping(PLAD) technique as a solution to resolve these issues. The viability ofour strategy is demonstrated by fabricating very-well controlled 60 nmpMOSFETs with PLAD in a standard architecture
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