A two-bit-per-cycle successive-approximation ADC with background offset calibration

摘要

In this paper we present a 10-bit, two-bit per cycles successive-approximation A/D converter (ADC). The circuit, operated at 60 MHz clock frequency, achieves a sampling frequency of 10 MHz, requiring only 6 clock cycles to accomplish a conversion. The ADC exploits three comparators to resolve two bits during each conversion cycle. To avoid the severe performance degradation due to offset mismatches among the comparators, we developed a novel background offset calibration technique. During the input signal sampling phase, when the comparators would otherwise be idle, we reconfigure the circuit to implement three one-bit per cycle, 8-bit successive-approximation ADCs, which within 8 conversion cycles measure the offset of each comparator. The effect of the comparator offset is then canceled in the digital domain. Simulation results confirm the effectiveness of the proposed solution, allowing to achieve 10 bits of resolutions even in the presence of large offsets in the comparators.