This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured low-density parity-check (LDPC) codes over additive-white Gaussian noise (AWGN) channels. The decoder, which has a serial architecture and moderate throughput, is a peripheral connected to the embedded PowerPC processor of a Xilinx Virtex-II Pro FPGA and is managed by the processor. This method of Hardware/Software implementation provides the maximum flexibility for the development and rapid prototyping of the hardware-based simulator system. The decoding algorithm proposed in this paper belongs to the class of min-sum with correction factor in which the correction factor updates with the log-likelihood ratio (LLR) values.
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机译：本文介绍了一种通用和嵌入式解码器的实现，用于评估加性白高斯噪声（AWGN）通道上的非结构化低密度奇偶校验（LDPC）码。该解码器具有串行架构和中等吞吐量，是连接到Xilinx Virtex-II Pro FPGA的嵌入式PowerPC处理器的外围设备，并由该处理器进行管理。这种硬件/软件实现方法为基于硬件的模拟器系统的开发和快速原型制作提供了最大的灵活性。本文提出的解码算法属于具有校正因子的最小和类别，其中校正因子以对数似然比（LLR）值更新。
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