Comparative analysis of the conventional 6T and recently proposed loadless 4T CMOS SRAM cells is performed. Based on HSPICE simulations for 0.18-μm technology, we compared the stability of the aforementioned cells to temperature and process (VTH, Leff, TOX) variations as well as the cells robustness in low-voltage operation. We found that at VDD = 1.2 V the loadless 4T cell has a 20% higher static noise margin (SNM) and 1.5 times lower sensitivity to the VTH fluctuations than the 6T cell. On the other hand, the 4T cell has a stronger read current degradation at reduced VDD. The analytical model for SNM calculation of the loadless 4T CMOS SRAM cell has been developed.
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