A GaAs pin-for-pin compatible replacement for the ECL 100474 4 KSRAM

摘要

In highest-speed cache memory systems, a RAM whose write cycletime is significantly slower than its read cycle time can pose asignificant problem to system designers. To solve this problem, aplug-in replacement for the industry standard 100474 ECL RAM has beendesigned, and has improved read access time and greatly improved writecycle time. It is designed to operate with no change in performance overa wide range of VEE power supplies, from -4.2 V to -5.7 V. The RAM isprocessed using a standard 3-layer metal process, FETs with twodifferent pinch-off voltages, and 4-inch GaAs wafers. A low-V_p FET with a nominal pinch-off of -0.15 V is used in theramcell's cross-coupled latch and also in the low-power super-buffers inthe periphery. A depletion FET with a nominal pinch-off of -0.65 V isused for the ramcell's pass gates and throughout the periphery. Toimprove yield, both row redundancy and column redundancy areimplemented. The RAM has an optional VBB input (previously a no-connecton the 100474) which sets the input threshold for all inputs. If thisVBB input is left floating or is tied to VEE, an internal switchconnects an internal VBB reference to all the input buffers