Ratio based hot-carrier degradation modeling for aged timingsimulation of millions of transistors digital circuits

摘要

A ratio based hot-carrier degradation model for aged timingsimulation of large CMOS circuits is presented. The model introducesgate-level representation and simply uses timing information. Theproposed model is implemented in the prototype simulator in which theaged timing is obtained from the fresh timing and the precharacterizedratio. The simulated results show that the simulation can be performedat the size and speed of logic simulation with comparable accuracy oftransistor-level simulator BTABERT