A buried capacitor DRAM cell with bonded SOI for 256 M and 1 GbitDRAMs

摘要

This paper describes a novel DRAM cell structure using bonded SOI.The cell capacitor is flexibly formed like a stack-capacitor, but buriedunder the silicon layer. Thus, both a large Cs and small cell size areobtained. Moreover, using a PMOS cell transistor whose back-surface isshielded by a cell plate, the cell leakage current is reduced to 1fA/cell, resulting in good data retention. Accordingly, a simple scalingof this structure realizes 256 M and 1 Gbit DRAMs