Design for reliability: A duty-cycle management system for timing violations

摘要

With continuous scaling of CMOS technology, a key issue for the microprocessor and application processor industries is the reliability of silicon. Two salient problems with silicon are Bias Temperature Instability (BTI), which increases the threshold voltage of MOSFETs, and Gate Oxide Breakdown (GOBD), which decreases the gate leakage resistance. Both pose severe limitations for sub-micrometer transistors. Threshold voltage and gate leakage current degradation affect setup/hold time violations and reduce system lifetime. To achieve a reliability tolerant system, we have developed a self-adaptive clock duty cycle controller (DCC) to avoid timing violations of critical paths of a microprocessor. Using lifetime prediction, we show how much the controller can extend system lifetime.