Low power LVDS circuit for serial data communications

摘要

With the advanced process, the supply voltage is decreased and power consumption is reduced dramatically. However, the power supply of LVDS receiver side is constrained, because the common mode voltage of LVDS is between 0.1 V and 2.4 V. By combining with design concepts of prior arts related to 1.8 V receiver circuit, a fully function of low power and high speed LVDS circuit is achieved. This presented LVDS transceiver has several advantages including easy to use and low power. The power consumption per unit without clock driver is only 8.68 mW/GHz, which has improved the performance by 38.2%. Due to the lower supply voltage of the receiver circuit, the power consumption per unit is 3.97 mW/GHz, with improvement of 134%. Besides, hysteresis circuit in this proposed circuit provides a better noise margin.