A 65 nm CMOS technology for mobile and digital signal processing applications

机译：适用于移动和数字信号处理应用的65 nm CMOS技术

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This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm2 and a SRAM memory density of 1.4 Mb/mm2 using a sub-0.49 μm2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

机译：本文介绍了一种65 nm CMOS技术，该技术使用sub-sub-sub器件实现了900 k-gates / mm ^{2 的逻辑密度和1.4 Mb / mm ^{2 的SRAM存储器密度。 0.49μm^{2 位单元。描述了用于移动产品（MP）的低成本技术选件和用于基于DSP的应用的高性能技术选件（HP）的关键特征。}}}

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《Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International》||p.665-668|共4页
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Chatterjee A.; Yoon J.; Zhao S.; Tang S.; Sadra K.; Crank S.; Mogul H.; Aggarwal R.; Chatterjee B.; Lytle S.; Lin C.T.; Lee K.D.; Kim J.; Hong Q.Z.; Kim T.; Olsen L.; Quevedo-Lopez M.; Kirmse K.; Zhang G.; Meek C.; Aldrich D.; Mair H.; Mehrotra M.; Adam L.; Mosher D.; Yang J.Y.; Crenshaw D.; Williams B.; Jacobs J.; Jain M.; Rosal J.; Houston T.; Wu J.; Nagaraj N.S.; Scott D.; Ashburn S.; Tsao A.;
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1. A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications [J] . Yih Wang, Hong Jo Ahn, Bhattacharya U., IEEE Journal of Solid-State Circuits . 2008,第1期

机译：采用65 nm超低功耗CMOS技术的1.1 GHz 12μA/ Mb泄漏SRAM设计，并具有针对移动应用的集成式减少泄漏功能
2. A 1.1 GHz 12 $mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications [J] . Yih Wang, Hong Jo Ahn, Bhattacharya U., IEEE Journal of Solid-State Circuits . 2008,第1期

机译：采用65 nm超低功耗CMOS技术的1.1 GHz 12 $ mu $ A / Mb泄漏SRAM设计，具有针对移动应用的集成式泄漏减少功能
3. All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology [J] . Salem Sanaz, Saneei Mohsen AEU: Archiv fur Elektronik und Ubertragungstechnik: Electronic and Communication . 2019,第期

机译：用于65 NM CMOS技术的USB应用的全数字时钟和数据恢复电路
4. A 65 nm CMOS technology for mobile and digital signal processing applications [C] . Chatterjee, A., Yoon, . 2005

机译：适用于移动和数字信号处理应用的65 nm CMOS技术
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8. Design of a CMOS,Fast Fourier Transform Module for Digital Signal Processing Applications. [R] . piekarski,joseph reid,joseph r. 1975

机译：用于数字信号处理应用的CmOs快速傅里叶变换模块的设计。

A 65 nm CMOS technology for mobile and digital signal processing applications

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