Fast multiplier schemes using large parallel counters and shiftswitches

摘要

We present novel fast parallel multiplier schemes. In contrast tothe full adder binary logic based traditional designs, we use(incomplete) large parallel counters and large shift switch compressors,which are built based on shift switch logic, a logic with shift switchesas logic elements performing modulo arithmetic operations on(non-binary) state signals. With the unique feature of shift switchlogic our parallel multiplier schemes have shown superiority in speedand in area compactness. This is provided through the use of astage-reduced partial product reduction network, the efficient signalinterconnection and the simplified final carry lookahead adder. Comparedto the well-known designs, our approach possesses higher regularity andsimplicity on circuit structures, characterized by both the recursiveshift switch networks which localize the major part of partial productreduction and the deliberated utilization of uneven arrival signalswhich minimize the delay of the multipliers