On test generation for interconnected finite-state machines-theoutput sequence justification problem

摘要

Test generation for synchronous sequential circuits can befacilitated by decomposing the circuit into a cycle free interconnectionof submachines, such that all feedback loops are included within thesubmachines. In this work, we describe a test generation procedure thattakes advantage of cycle free circuit decomposition. The paper focuseson one of the subproblems of the test generation problem, the outputsequence justification problem. We propose a solution to this problemand show how it can be incorporated into a test generation procedure