PROCESSOR TEST INSTRUCTION SEQUENCE GENERATION METHOD, PROCESSOR TEST INSTRUCTION SEQUENCE GENERATION PROGRAM, AND PROCESSOR TEST INSTRUCTION SEQUENCE GENERATION DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a technique capable of verifying an instruction sequence execution result using a guaranteed register value even if an SISD instruction and an SIMD instruction are mixed up.SOLUTION: A processor test instruction sequence generation method includes the steps of: classifying registers used to execute test instructions into two register groups, and dividing the registers such that a register in the first register group is allocated to a first instruction for setting a value of at least a second register to an indefinite value at a time of rewriting a first register, and that a register in the second register group is allocated to a second instruction for accessing a plurality of registers at one execution; generating the test instructions; and correcting a designated register according to a calculation type field.