A hardware/software concurrent design for a real-time SP@ML MPEG2video-encoder chip set

摘要

This paper presents a design for a real-time MPEG2 SP@MLvideo-encoder chip set. Its main features are: hardware/softwarepartitioning based on a software encoder analysis, and a pipelinearchitecture where hardware and software interact closely and smoothly.We use a hardware/software concurrent design technique with fastverification to avoid major modifications at architectural and RTLlevels. The chips were successfully fabricated with 0.5-μm CMOStechnology