Approximate analysis of average performance of (σ,ρ)regulators

摘要

A study is made of the average delay and the blocking probabilityof a regulator with a finite buffer size fed with Poisson and batchPoisson streams. The blocking probability depends only on σ andB through σ+B where B is the buffersize and σ is expressed as an integer multiple of the packet size.The provision of regulator buffers allows flexibility in the trafficcontrol such that incoming traffic can be delayed during minor overloadsand rejected during major overloads. In addition, the provision ofregulator buffers allows the use of smaller network buffers, which aretypically more expensive due to high-speed operation. Also studied isthe packet departure process from the regulator. A four-parameterdescriptor (σ,ρ, C_a2,λ)is proposed to characterize the output process of the regulator. Inaddition, formulas are proposed to construct the four-parameterdescriptor for the output process of the multiplexer. Such descriptorsmay be useful in multihop situations. Simulation results indicate thatthe proposed approximations are close to the simulated values