Compatibility of candidate high permittivity gate oxides with frontand backend processing conditions

摘要

The need for new, high permittivity dielectrics for gate stacks inCMOS devices is now well recognized. The timescales for the requirementsis laid out in recent issues of the Semiconductor Industry AssociationRoadmap. The most pressing requirement is for low powered MOSFETs.Research into high permittivity candidate dielectrics has thereforeproceeded with urgency over the past 3 years. In general, two approachesare possible. Industry would prefer the direct replacement of SiO₂ as the gate dielectric, while making relatively few changes tothe subsequent process conditions. This would require that thealternative dielectric be capable of surviving the high temperaturerapid thermal anneals (typically over 1000° C) required for dopantactivation, in addition to the reducing backend anneals used to ensurelow contact resistances for the interconnect structures. An alternativeapproach is to determine optimum process conditions for the gatedielectric, and adapt the CMOS process flow to accommodate this process.Relatively few resources have to date been expended to determine whetherdirect replacement is a possibility. This question is thus the researchtopic addressed in this paper. We address the question by establishingthe conditions for thermodynamic stability of candidate dielectrics atelevated temperature, and the conditions under which specific reactionsoccur. We confirmed our reaction models by measuring the properties ofappropriate MOS capacitors after high temperature processing