首页> 外文会议>Electronics Manufacturing Technology Symposium, 1996., Nineteenth IEEE/CPMT >A method for the measurement of chip to leadframe adhesion in LOCpackages
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A method for the measurement of chip to leadframe adhesion in LOCpackages

机译:一种LOC中芯片与引线框附着力的测量方法。包装

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Adequate die-to-leadframe adhesion is necessary for LOC packageintegrity during and after manufacturing process. Poor adhesion mayresult in a variety of defects such as die adhesion failure, marginalwire bond, broken wire, exposed wire at the surface of the plasticencapsulated package, and bent leads, ultimately leading to electricalfailure [1,2]. In this paper, a technique to measure the adhesion ofleadframes to electronic chips in LOC type packages is described. Inthis method, the leads on opposite sides of the die are pulled using auniversal materials tester (e.g., Instron). We found that samplepreparation and measurement equipment set-up were critical to theconsistency and repeatability of the measurements. A comparison ofmeasurements on packages bonded with three different materials ispresented. Minimum bonding forces required for best yields weredetermined for these three types of chip-to-leadframe bonding materials.Using this information, we were able to rank materials with respect totheir relative adhesion characteristics
机译:LOC封装需要足够的管芯与引线框之间的粘合力 制造过程中和制造后的完整性。附着力差可能 导致各种缺陷,例如芯片粘合失败,边缘 塑料表面的金属丝键合,金属丝断裂,金属丝裸露 封装的封装和弯曲的引线,最终导致电气 失败[1,2]。在本文中,一种测量附着力的技术 描述了采用LOC型封装的电子芯片引线框。在 这种方法是使用 通用材料测试仪(例如Instron)。我们发现了那个样品 准备和测量设备的设置对于 测量的一致性和可重复性。比较 用三种不同材料粘合的包装的测量值是 提出了。获得最佳产量所需的最小结合力为 确定了这三种类型的芯片到引线框接合材料。 利用这些信息,我们能够对以下方面的材料进行排名 它们的相对粘附特性

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