Selection of base substrate material for design against interfacialdelamination for a multilayered system-on-package (SOP) structure

摘要

System-On-Package (SOP) can reduce package size, increasefunctionality and improve performance at lower costs by embeddingpassives in a multilayered high-density wiring (HDW) structure. Due tothe stringent warpage requirement for processing such a package, newbase substrate materials are being explored with high modulus. Thesubstrate will also have a CTE that is close to that of the die. Thematched CTE will facilitate no-underfill attach flip-chips on SOPsubstrates. One major concern with the high-modulus“matched” CTE substrate is the potential interfacialdelamination between different dielectric and metallization layersbuilt-up on top of the base substrate. This research examines thepossibilities of interfacial delamination in such a multilayeredpackaging structure under thermal loading. The objective of this paperis to evaluate the possibility of interfacial delamination of the newSOP integrated substrates with a primary focus on metallization copperand dielectric layer interface. An analytical model and numerical modelhave been developed to calculate the energy release rate of multilayeredstructures under thermal load. Based on the analysis results, a baselayer material has been selected from a group of candidate materials.With this material as the base layer, the substrate has the minimumchance for a delamination to grow. The interfacial fracture toughness ofcopper/ViaLuxTM 81 PDDF has been measured. The energy releaserate obtained from the analysis was compared with the interfacialfracture toughness, and the results indicate that there is minimaldelamination growth under the given thermal load conditions. Based onanalysis results, design recommendations for improving thermomechanicalreliability are proposed