Single level integrated packaging modules for high performanceelectronic systems

摘要

In this paper, we introduce a novel packaging scenario that aimsto integrate or eliminate the existing multilevel packaging hierarchiestowards single level integration. The new approach is actually anextension of VLSI technology where standard IC processes were pursued inthe whole fabrication sequence. Test samples were made successfully. Themodule and interconnect structures, integration process, and electricalperformance were studied theoretically and experimentally. Properties ofsignal propagation and coupling from chip to chip were simulated andmeasured in frequency domain as well as in time domain. It shows thatoff-chip communication with several Gb/s data rate is possible in suchmodules