Meeting the heat removal requirements of `tiled' compliant waferlevel packages

摘要

The `tiling' of wafer level packages yields the maximum increasein the performance and the packing efficiency. The limitations on the`tiling' are posed by the capability of removing the heat from all theapplications ranging from low power to high power. This paper presents athorough analysis of the optimum thermal design of the wafer levelpackage and the system assembly to meet the high performance heatremoval requirements while maintaining the `tiled' assembly. The resultsindicate that even with heat sink fin aspect ratio of 100:1, it is notpossible to remove the heat from the `tiled' high performance waferlevel package assembly. An optimum methodology is developed to determinethe placement of components on the beard such that the heat can beremoved without sacrificing the `tiled' assembly. By using thismethodology, the fin aspect ratio of 25 and 50 is sufficient to meet thecost performance and high performance applications' heat removalrequirements, respectively