首页> 外文会议>IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits >An Electrical Failure Analysis (EFA) Flow to Quantitatively Identify Invisible Defect on Individual Transistor: Using the Characterization of Random Dopant Fluctuation (RDF) as an Example
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An Electrical Failure Analysis (EFA) Flow to Quantitatively Identify Invisible Defect on Individual Transistor: Using the Characterization of Random Dopant Fluctuation (RDF) as an Example

机译:电气故障分析(EFA)流动以定量识别单个晶体管上的无形缺陷:使用随机掺杂剂波动(RDF)的表征作为示例

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摘要

An EFA flow is proposed to characterize a defective PMOS transistor that suffered abnormal high threshold voltage (Vth). Forward-Reverse (F-R) measurements observe asymmetric electrical characteristics in Id-Vg curves. Further body effect measurements confirm that the asymmetry symptoms are attributed to abnormal dopant concentration on well region, where RDF is suspected. Calculation shows that the well concentration of defective transistor is 1.8x of the well concentration of reference transistor. Technology Computer Aided Design (TCAD) and Simulation Program with Integrated Circuit Emphasis (SPICE) simulations all show that this 1.8x of well concentration will lead to a about 190 mV Vtsat increase, which explains 46% of the total Vtsat increase at T0. This study shows that RDF limits yield and performance on advanced IC technology. With the adopting of low implantation process and Fin structure, FinFET technology exhibits significant reduction on Vth variability and reaches unprecedented low value on minimum operating voltage (Vccmin).
机译:提出了一种EFA流程,以表征遭受异常高阈值电压(Vth)的PMOS晶体管。向前反转(F-R)测量观察ID-VG曲线中的不对称电气特性。进一步的体效应测量证实,不对称症状归因于孔区域的异常掺杂剂浓度,其中涉及RDF。计算表明,缺陷晶体管的孔浓度是参考晶体管的孔浓度的1.8倍。技术计算机辅助设计(TCAD)和仿真程序,具有集成电路强调(SPICE)模拟,所有表明这1.8倍的井浓度将导致约190 mV的VTSAT增加,这解释了T0的vTSAT总增加的46 %。本研究表明,RDF限制了高级IC技术的产量和性能。随着低植入过程和鳍结构的采用,FinFET技术对VTH变异性显着降低,并且在最小工作电压(VCCMIN)上达到前所未有的低值。

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