首页> 外文会议>2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits >An Electrical Failure Analysis (EFA) Flow to Quantitatively Identify Invisible Defect on Individual Transistor: Using the Characterization of Random Dopant Fluctuation (RDF) as an Example
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An Electrical Failure Analysis (EFA) Flow to Quantitatively Identify Invisible Defect on Individual Transistor: Using the Characterization of Random Dopant Fluctuation (RDF) as an Example

机译:电气故障分析(EFA)流程,以定量识别单个晶体管上的隐形缺陷:以随机掺杂物波动(RDF)的特征为例

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摘要

An EFA flow is proposed to characterize a defective PMOS transistor that suffered abnormal high threshold voltage (Vth). Forward-Reverse (F-R) measurements observe asymmetric electrical characteristics in Id-Vg curves. Further body effect measurements confirm that the asymmetry symptoms are attributed to abnormal dopant concentration on well region, where RDF is suspected. Calculation shows that the well concentration of defective transistor is 1.8x of the well concentration of reference transistor. Technology Computer Aided Design (TCAD) and Simulation Program with Integrated Circuit Emphasis (SPICE) simulations all show that this 1.8x of well concentration will lead to a about 190 mV Vtsat increase, which explains 46% of the total Vtsat increase at T0. This study shows that RDF limits yield and performance on advanced IC technology. With the adopting of low implantation process and Fin structure, FinFET technology exhibits significant reduction on Vth variability and reaches unprecedented low value on minimum operating voltage (Vccmin).
机译:提出了EFA流程以表征遭受异常高阈值电压(Vth)的有缺陷的PMOS晶体管。正向(F-R)测量在Id-Vg曲线中观察到不对称的电气特性。进一步的身体效应测量结果证实,不对称症状归因于怀疑是RDF的孔区域的异常掺杂物浓度。计算表明,缺陷晶体管的阱浓度是参考晶体管的阱浓度的1.8倍。技术计算机辅助设计(TCAD)和带有集成电路重点的仿真程序(SPICE)仿真都表明,这一1.8倍的阱浓度将导致Vtsat大约增加190 mV,这解释了在T0时总Vtsat的46%。这项研究表明,RDF限制了先进IC技术的良率和性能。由于采用了低注入工艺和Fin结构,FinFET技术显着降低了Vth的可变性,并在最小工作电压(Vccmin)上达到了前所未有的低值。

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