首页> 外文会议>IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits >Effect of Cu barrier from TaN/Ta Deposition barrier(DD) TaN/Etching/Ta Deposition barrier(DED) on Cu EM reliability
【24h】

Effect of Cu barrier from TaN/Ta Deposition barrier(DD) TaN/Etching/Ta Deposition barrier(DED) on Cu EM reliability

机译:TaN / Ta沉积势垒(DD)和TaN /蚀刻/ Ta沉积势垒(DED)对Cu势垒的影响

获取原文

摘要

Electromigration(EM) is one of the main failure modes in copper interconnect evaluation. Good barrier step coverage and good ECP Cu gap-filling in the via process have produced better EM performance of copper interconnect, therefore, we did a different Cu barriers reliability discussion, TaN/Ta Deposition barrier(DD) & TaN/Etching/Ta Deposition barrier(DED). In this paper, we analyzed the difference between barriers of DD / DED test results and the process on via upstream (Figure 1-A / 1-B), and the EM effect of the difference between the bottom barrier and sidewall barrier of the DD and DED.
机译:电迁移(EM)是铜互连评估中的主要故障模式之一。在通孔工艺中,良好的势垒台阶覆盖率和良好的ECP铜间隙填充可产生更好的铜互连EM性能,因此,我们进行了不同的铜势垒可靠性讨论,即TaN / Ta沉积势垒(DD)和TaN /蚀刻/ Ta沉积屏障(DED)。在本文中,我们分析了DD / DED测试结果的势垒与通孔上游工艺之间的差异(图1-A / 1-B),以及DD的底部势垒和侧壁势垒之间的差异对EM的影响和DED。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号