4-Bit Vedic Multiplier with 18nm FinFET Technology

摘要

The Vedic multiplier has a very fastest arithmetic operation and less complex than a multiplier. The Vedic multiplier is used to simplify the multiplication process and delay. If the Vedic multiplier is designed by using CMOS transistors, the circuit will raise problem. To overcome this issue, the Gate Diffusion Input (GDI) logic has been implemented in this paper using FinFET technology. Here, GDI logic is used to reduce the transistor count of the circuits. However, in these process, two types of design approaches are considered. The first type approach aims to implement the 4-bit Vedic multiplier (Design 1) using GDI based AND, half adder, and full adder circuits. Second type approach is intended to design a 4-bit Vedic multiplier (Design 2) by using GDI based 2-bit Vedic multiplier, half adder and 4-bit Ripple carry circuits. In these, the circuit performance factors like average power, delay and transistor count, and circuit area are considered.