As Moore’s law hits physical limits, monolithic 3D (M3D) integration based on fine-grained monolithic inter-tier vias is emerging as a promising technique to continue performance, power, and area improvements. However, the design of a reliable power delivery network (PDN) for M3D integrated circuits (ICs) is a formidable challenge due to higher power and current densities. In addition, compared to traditional designs, interconnects in M3D designs are more susceptible to electromigration and stress migration. Yield loss resulting from the power-supply noise (PSN) in functional and testing mode is also a major concern for M3D ICs. In this paper, we describe recent research efforts that provide solutions to mitigate these reliability concerns in M3D ICs.
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