Test Challenges of Providing Low Phase Noise Reference Clock Signal with ATE Platform

摘要

Device that consist of high-speed Analog-to-Digital Converts (ADC) or high-speed interfaces require the input of very low phase noise (below 100 femtoseconds) of reference clock signals. In general, Automatic Test Equipment (ATE) face challenges in measuring certain items. This paper explains reasons why low phase noise clock signals are required for high-speed ADC and discussed the operation concepts and implementation methods of all-digital phase locked-loop (ADPLL). ADPLL exhibits various strengths, with the primary ones being its high precision, high resolution, and jitter cleaner. A conventional testing, precision bench instruments are employed to fulfill the test requirements. By contrast, the integrated testing Automatic Test Equipment platform of V93000 WSPS-PD offers a solution with more satisfactory performance in mass-production testing.