首页> 外文会议>International Conference on Electron Devices and Solid-State Circuits >Composite FPGA-based Accelerator for Deep Convolutional Neural Networks
【24h】

Composite FPGA-based Accelerator for Deep Convolutional Neural Networks

机译:用于深度卷积神经网络的基于FPGA的复合加速器

获取原文

摘要

Convolutional neural network (CNN) can achieve high prediction accuracy while they built complex models; however, high power consumption, memory demands, and bandwidth resource consumption by the models are creating enormous challenges in their actual deployment. To achieve the rapid prediction capabilities of high-precision models, a modified convolutional neural network model based on the GoogLeNet model has been proposed in this work, and a composite-structure convolutional neural network hardware accelerator compatible with the parallel computing model has been designed. An experimental model based the modified structure has been established and CIFAR-10 dataset was used to evaluate the prediction accuracy. The accelerator achieved 663 FPS peak performance with a 9.06% error rate, and was implemented on a Xilinx VC709. Compared to CPU and GPU, its energy efficiency increased by a factor of 7.1 and 1.9, respectively, achieving a high-precision complex network computing acceleration.
机译:卷积神经网络(CNN)在构建复杂模型时可以实现较高的预测精度;但是,模型的高功耗,内存需求和带宽资源消耗正在其实际部署中带来巨大挑战。为了实现高精度模型的快速预测能力,本文提出了一种基于GoogLeNet模型的改进的卷积神经网络模型,并设计了与并行计算模型兼容的复合结构卷积神经网络硬件加速器。建立了基于改进结构的实验模型,并使用CIFAR-10数据集评估了预测精度。该加速器在Xilinx VC709上实现,具有663 FPS的峰值性能,错误率9.06%。与CPU和GPU相比,其能效分别提高了7.1和1.9倍,实现了高精度的复杂网络计算加速。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号