Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits

摘要

In this paper, we propose a stand-by interconnect test method of 3D stacked ICs with IEEE 1149.1 test circuits embedded in dies. Resistive open defects are detected after shipping to a market by the test method that occur at input interconnects of dies operating at a stand-by mode. Feasibility of the stand-by tests is examined by SPICE simulation. It is shown that a resistive open defect of 83 kΩ and above can be detected at a test speed of 20MHz by the test method.