System and method for parallel testing of IEEE 1149.1 compliant integrated circuits

摘要

The present invention is generally related to a system and method for conducting parallel testing of IEEE1149.1 compliant integrated circuits hardware via comparing results generated by integrated circuits under evaluation in accordance with IEEE1149.1 JTAG/IEEE standard test access port and boundary scan architecture provisions, with a master reference signal to determine whether the integrated circuit is functioning properly. There is provided a multi-input scan chain select unit for receiving a selected group of integrated circuit test data inputs. There is provided a comparator unit for comparing each of the selected integrated circuit test data inputs with a predetermined reference signal and determining whether they are the same or not. Malfunctioning integrated circuits are identified based upon results of the comparison.