Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL

摘要

In this paper, we analyze the mechanism of the phase noise generation caused by the mutual interference of two oscillators and investigate the control method of this issue. At first, in the cascaded phase-locked loop (PLL) circuit, we show the interference noise model between oscillators based on the linear model. From the simulation results, we present the possibility of the phase noise generation within the PLL bandwidth caused by this interference. In our analysis, the timing adjustment between the first-stage PLL and the second-stage PLL is shown to be effective for the control of noise generation. In addition, our simulation results show that the internal injection loops between the first and the second PLL's oscillators would degrade the influence of the interference between oscillators. Next, we designed and fabricated the testchip for the verification of our analysis on the 0.18-μm standard CMOS process. The oscillation phases of two oscillators in the cascaded PLL can be changed externally by the variable delay line between the first and the second PLLs. From the measurement result, we confirmed that the jitter generation caused by the mutual interference between oscillators was controlled by the timing adjustment of oscillators.