Low Power Novel 10T SRAM with Stabled Optimized Area

摘要

The high demand for memory devices by decreasing power consumption is significant. SRAM has been under its renewal phase by enduring the ever-increasing delay along with supporting low power applications. A New 10 transistor (lOT) SRAM cell architecture has been proposed as explanations for the limitations of conventional SRAM models, in this paper. The proposed cell excels, in particular, three aspects: 1) data overwriting, 2) low power consumption, and 3) Improved area. The second value makes it particularly appropriate for a SRAM is stability. We have simulated and validated its performance by using 45nm predictive technology model (PTM).