Sense amplifiers in low power and high performance SRAMs

摘要

In described examples, a static random access memory (SRAM) includes an array of storage cells and a first sense amplifier (208). The array of storage cells is arranged as rows and columns. The rows correspond to word lines, and the columns correspond to bit lines. The first sense amplifier (208) includes a first transistor (410) and a second transistor (412). The first sense amplifier (208) is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier (208) is configured to increment a body bias of the first transistor (410) a first time. In response to the body bias of the first transistor (410) being incremented, the first sense amplifier (208) is configured to provide a second read of the first storage cell.