NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines

摘要

The 3D design of SRAM LLCs has made the thermal problem, even more, sever and therefore incurs more leakage energy consumption compared to conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose a runtime cache architecture called NIZCache. The core idea of NIZCache is to use the non-uniform distribution of the accesses, invalid lines, and zero-value lines in banks of last level cache for decreasing both dynamic and leakage energy. The proposed architecture that is based on non-uniform cache architectures (NUCA) disables cache banks that have low accesses and high invalid and zero lines and leads to high energy-efficiency. The Experimental results show that the proposed method improves the energy-delay product by about 17% on average under PARSEC benchmarks compared to previous work.