In this paper, a coded modulation scheme using extremely sparse low-density parity-check (LDPC) codes is proposed for the stored signal of triple-level-cell (TLC) NAND flash, where both the encoding and the decoding complexity can be significantly reduced with the advantage of the extremely sparse code graph. In order to enhance the performance of decoder, iterative detection decoding (IDD) is introduced to extract the extrinsic information from the symbol detector, and the cooperative non-Gray mapping is also designed. In addition, for error floor lowering, an interleaver is inserted to ensure the cascaded degree-2 variable nodes are separated to individual symbols. The simulation results show that the proposed coded modulation scheme can provide a practical error floor performance with a low decoding complexity.
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