A novel sequence latched synchronizer design interface for asynchronous clock domains

摘要

The paper introduces a novel synchronization scheme for digital circuits considering both the elimination of metastability and latency that occurs during the data transfer between asynchronous clock domains. An architectural approach that overcomes the amount of duplication over conventional speculative methods is proposed. The method reliably transfers the data between flip-flops during synchronization cycles. We present an FSM model that achieves tremendous improvement in hardware costs. A further analysis on system latency with an additional source synchronous clock at a higher frequency completely eliminates it. Synthesis results verify our approach by showing a 50% reduction in hardware and zero latency.