A 0.028mm 19.8fJ/step 2-order VCO-based CT ΔΣ modulator using an inherent passive integrator and capacitive feedback in 40nm CMOS

摘要

This paper presents an OTA-less 2-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO's inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 19.8fJ/step with 68.6dB SNDR over 6MHz BW.