6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance

摘要

As we move to higher data rates, the performance of clock and data recovery (CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes their performance sensitive to changes in jitter caused by PVT variations, crosstalk or power supply noise. This is because the gain of a BB-PD depends on the CDR input jitter, causing the loop gain of the CDR to change if the jitter magnitude or spectrum varies. This problem is illustrated in Fig. 6.7.1 where small jitter leads to excessive loop gain and hence to an underdamped behaviour in the CDR jitter tolerance (JTOL), while large jitter leads to insufficient loop gain and hence to low overall JTOL. To prevent this, we propose a CDR with an adaptive loop gain, KG, as shown in Fig. 6.7.1.