首页> 外文会议>Conference on space telescopes and instrumentation >Studies of prototype DEPFET sensors for the wide field imager of Athena
【24h】

Studies of prototype DEPFET sensors for the wide field imager of Athena

机译:用于雅典娜广域成像仪的DEPFET原型传感器的研究

获取原文

摘要

The Wide Field Imager of the Athena telescope will combine an excellent spectroscopic performance and high count rate capability with a large field of view. For these purposes, its focal plane consists of two complementary detectors, using DEPFET active pixel sensors. One is the high count rate detector with a small field of view, which has to be operated with a readout speed of 80 μs per frame. In contrast, the large area detector will cover a large field of view and has to be read out with a frame rate ≤ 5 μs. Its sensitive area is covered by four identical active pixel arrays, consisting of 512 × 512 pixels, each. Since a column parallel readout will be used, 512 pixels are connected to one single channel of a readout ASIC. The readout will be accomplished by either sensing a voltage step on the source node or a change of the transistor drain current. The former so-called source follower mode requires long settling times - proportional to the load capacitances - but can cope with local inhomogeneities. Alternatively, the latter so-called drain current mode provides a fast readout - independent to the load capacitance - but implicates a higher sensitivity on local variations of the DEPFETs bias currents. Both modes are implemented in the VERITAS 2.1 readout ASIC and were studied with 64 × 64 pixels arrays. Drain current devices could be operated with significantly smaller settling times but suffer from a slightly increased noise at similar shaping times in comparison to the source follower ones. By using an optimized timing with dedicated settling and shaping times, the devices of both modes feature a comparable spectral performance.
机译:雅典娜望远镜的宽视场成像仪将结合出色的光谱性能和高计数率功能,并具有广阔的视野。为此,它的焦平面由两个互补的检测器组成,使用DEPFET有源像素传感器。一种是视野较小的高计数率检测器,必须以每帧80μs的读出速度进行操作。相反,大面积检测器将覆盖大视野,并且必须以≤5μs的帧速率读取。它的敏感区域被四个相同的有源像素阵列覆盖,每个像素阵列由512×512像素组成。由于将使用列并行读出,因此将512个像素连接到读出ASIC的一个通道。读出将通过检测源节点上的电压阶跃或晶体管漏极电流的变化来实现。前者所谓的源极跟随器模式需要较长的建立时间-与负载电容成正比-但可以应对局部不均匀性。可替代地,后一种所谓的漏极电流模式提供了独立于负载电容的快速读出功能,但对DEPFET偏置电流的局部变化具有更高的灵敏度。两种模式均在VERITAS 2.1读出ASIC中实现,并使用64×64像素阵列进行了研究。与源极跟随器相比,漏极电流器件可以在更短的建立时间下运行,但在相似的整形时间处噪声会稍有增加。通过使用具有专用建立时间和整形时间的优化时序,两种模式的器件均具有可比的频谱性能。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号