Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components

摘要

As the device size decreases, the reliability degradation caused by soft-errors and multiple component error due to a single soft-error are becoming serious problems in VLSIs. In this study, we propose a method to synthesize single soft-error tolerant datapaths based on soft-error detection by duplication and comparison and correction by retry. Under the assumption that a single soft-error does not affect beyond a certain spatial and time range, we consider adjacency constraint between components in datapath. The major contributions of this research are (i) adjacency constraint between components to employ appropriate soft-error tolerance and achieve more effective use of resources and (ii) an ILP based resource binding considering adjacency constraint to minimize the increment of the chip size due to introducing the new constraint.