Latchup holding voltages and trigger currents in an SOI technology

摘要

This paper investigates holding voltages and trigger currents in a Silicon-on-Insulator technology. These parameters can be used in automated layout checks. Via a new measurement method, where the well-bias of the test structures is varied with regard to the bias of the emitters of the thyristor, a strong dependency on the emitter distance, and a weak dependency on the well tap distance is observed. The holding voltages are compared to a low-Ohmic and high-Ohmic variant of the same technology node. Trigger currents of a layout with a variable well tap length are investigated. A model for the effective resistance is developed, incorporating the increased resistance for longer current paths by segmenting the current flow area. The performance of the model and possible applications are discussed.