IEC 61131-3 compliant PLC structure based on FPGA multi-core solution

摘要

The paper discusses the design process of a full programmable logic controller implemented by means of FPGA device. The PLC is compliant with EN 61131-3 standard. It is equipped with a programmer that allows to transfer a program to the program memory of the controller, and the I/O controller which allows the exchange of information with the outside world, i.e. the signal modules. Some interesting aspects of instruction list and hardware architecture designing are presented, e.g. the PLC structure with a particular emphasis on central processing unit and memory map. The PLC is developed using one FPGA device as a combination of dedicated logic and soft-processor based parts. This gives an opportunity to develop interesting solutions. For example, using dual port RAM gives an opportunity to implement bit/word access without the necessity of masking bits. The paper presents a short description of a designed and written simple integrated development environment.