High-speed architecture of the CABAC probability modeling for H.265/HEVC encoders

摘要

In hardware video encoders, the throughput of the entropy coding stage can limit the support of high-quality and high-resolution videos. This paper presents an FPGA-oriented optimization method which increases the clock frequency of the probability modeling stage of the multi-symbol Context Adaptive Binary Arithmetic Coder (CABAC). The method leverages the unary code to represent probability states updated while coding successive binary symbols directed to the CABAC. Implementation results show that the maximal frequency can be increased by about 14-19% for designs implemented in FPGA devices.