Errors due to radiation effects are a growing reliability concern for modern aerospace systems. In particular, single-event transients (SETs) and single-event upsets (SEUs) due to charged ion strikes in integrated circuits (ICs) have resulted in data corruption and operational failures in space systems. As IC feature sizes continue to shrink, the vulnerability of electronic systems worsens as smaller and smaller amounts of single-event charge become sufficient to alter the voltages on critical circuit nodes. Modern radiation-hardened systems rely on radiation-hardened-by-design (RHBD) techniques to reduce radiation vulnerability in commercially available IC processes without requiring changes to the manufacturing process itself. Several new RHBD concepts that are specifically applicable to analog and mixed-signal circuits have been developed in recent years. The RHBD concept of ¿¿¿node splitting¿¿¿ to create parallel signal paths has been shown to improve single-event hardness in switched-capacitor and continuous-time analog and mixed-signal circuits. Examples of HNS (hardening via node splitting) include dual- and quad-path switching capacitor signal processing circuits, and peeled layouts in operational amplifiers and comparators. This paper provides an overview of the HNS concept, with an emphasis on two new techniques currently under development: massively multiple peeled layouts (MMPL), and smart peeling. A circuit with a peeled layout is split into two or more parallel subcircuits that are connected at the input(s) and output(s), but with separate internal nodes. Absent any radiation effects, components are sized such that the peeled circuit behaves almost identically to the original unpeeled circuit in terms of electrical performance. However, in the event of an ion strike that upsets one of the subcircuits, the remaining subcircuit(s) will continue to operate normally and thereby mitigate the resulting single-event transient at the output. MMPL and smart peelin- are newly developed refinements of the basic peeled layout concept. Massively multiple peeled layouts take advantage of the layout restrictions imposed by increasingly constrained design rules in very deep submicron IC processes. In an MMPL design, critical subcircuits and sensitive nodes may be split into 4, 8, 16, or more parallel paths to provide additional hardness benefits. The MMPL technique appears particularly well suited to critical global subcircuits such as bias circuits and voltage references. Smart peeling operates in a different fashion. Instead of the brute-force ¿¿¿wire-ORing¿¿¿ of two or more signal paths into completely separate subcircuits, a circuit with smart peeling only has select internal nodes separated such that the struck path is disabled by the collected charge, leaving the remaining path to maintain the integrity of the signal. Circuit examples of MMPL and smart peeling are presented, with simulation results that illustrate the efficacy of these concepts in hardening continuous-time AMS circuits without significant penalties in overall circuit area, power, or electrical performance.
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