Buildup PWB (Printed Wiring Boards) for semiconductor package is widely used which is laminated the buildup materials onto the core materials (high Tg FR4, FR5 or BT). Generally, epoxy based buildup materials is used without glass cloth for the package of ASIC's(Application Specific Integrated Circuits), CPU's, GPU's, and other IC's that require large numbers of I/O(input/output) circuits because it can form a small-diameter vias and fine conductive patterns formed. FC-BGA is dominant position in the market and it is used for the microprocessor package on a personal computer. In higher-performance MPU and ASIC of supercomputers and high-end server applications, multi-layered is progressing. 6+4+6 and 8+8+8 layer structure has been proposed as a high multilayer substrate.[1] To fabricate very fine traces and spaces for the build-up layer, either M-SAP (Modified-Semi Additive Process) with ultra-thin copper foil on removable carriers or SAP (Semi Additive Process) with electro less copper plating or sputtering are used. Also M-SAP is widely used to have a downsizing of the core layers. On the other hand, smaller and thinner size of package is required in the application processor and baseband processor mounted on a digital mobile devices such as smart phones and tablet PC. FC-CSP is adapted due to fewer number of I/O. In the package of the mobile system, rigid substrate is used for via machining, especially in laser from a cost point of view. A prepreg which reinforced with glass cloth are stacked. The FC-CSP, since is progressing thinner board equipment, thin core + the build-up structure is typically, 1+2+1 structure and 2+2+2 structure has become widespread. [1] In the memory applications of relatively small wiring density, coreless build-up structure of a three-layer using prepreg is being applied on FC-CSP. The FC-CSP wiring formation, subtractive process is used for forming a circuit by removing only the non-circuit portion of the copper foil of the entire - ubstrate surface by etching. In these build-up board, the development of a copper foil is desired to the next generation to achieve a good adhesion, fine line with smooth surface. The development of small form factor module is still ongoing especially for the portable handheld products, such as smart phone and tablet. Higher density wiring technologies have been required to reduce the size and the assembly area of substrate. Build up wiring technology is one of the key to have higher density with small size. Lots of wiring technologies has been announced with finer wiring for 3D, 2.5D and 2.1D interposer application as a leading edge technology [2-8]. However in the real world of consumer electronics, cost is always very sensitive for high volume applications. Therefore the development speed is relatively slow, unlike a semiconductor applications. To accelerate the development speed of PWB (Printing wiring board) applications, nano scale profile copper foil is proposed. This paper is introducing newly developed treatment technology for copper foil which enable ultra-low profile by conditioning a copper surface in nano scale. A fine patterning and adhesion performance are demonstrated. Since adhesion test, slightly lower adhesion is confirmed even though cohesive fracture mode on nano scale profile foil. To understand this behavior, FEM (Finite Element Modeling) is used in terms of stress on nano scale profile foil. The simulation model is investigated in this paper. From the result with realistic copper foil model and localized prepreg parameter, larger maximum principal stress which is concentrated near the interface between prepreg and the copper foil is conducted for nano scale copper foil.
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