CMOS logic circuits; FIR filters; adders; energy conservation; energy consumption; logic design; low-power electronics; multiplying circuits; 4-tap digital FIR filter; CMOS logic design; SBL; array multiplier; carry save adder; carry save multiplier; charge recovery logic; clock frequency; digital circuit; digital system; energy consumption; energy efficiency; enhanced boost logic; frequency 180 MHz to 1 GHz; industry standard cadence virtuoso-64; low power FIR filter; subthreshold boost logic design; Adders; Finite impulse response filters; Indexes; Integrated circuit reliability; Logic gates; Rails; Boost logic; Enhanced boost logic; Evaluation stage; Gate overdrive capability; Sub-Threshold logic;
机译:用于ECG信号降噪的吠陀设计FIR滤波器的低功耗和低面积VLSI实现
机译:逻辑优化技术的设计与实现MAC基于FIR滤波器
机译:FIR滤波器实现中的分布式算术单元新型低功耗架构设计
机译:使用子阈值升压逻辑设计实现低功耗FIR滤波器
机译:超低功耗数字亚阈值逻辑设计。
机译:GaN基三相有源电力滤波器的设计与实现
机译:使用低功耗和高速倍增器和加法器的FIR滤波器的设计与实现